Abstract

Data-centric applications continue to be limited by the memory wall. Logic-in-Memory (LiM) architectures based on non-volatile memories (NVMs), such as memristors, offer a promising solution by enabling in-memory computation and eliminating costly data movement. While several approaches leveraging memristor-aided logic (MAGIC) operations have been proposed, many fail to fully exploit the parallelism and spatial efficiency of memristor crossbars, especially under physical design constraints. In this paper, we propose a parallelism-driven, area-aware look-up table (LUT)-based mapping framework of arbitrary logic circuits into a memristor crossbar using MAGIC operations. We present a crossbar-aware floorplanning strategy that leverages topological LUT information to enable two-directional parallel computation (ie, HNOR and VNOR), thereby maximizing computational LUTs with minimal execution cycles. We formulate an integer linear programming (ILP) approach to define the placement of each LUT and its fanin locations, improving routability while preserving parallelism. Moreover, we introduce our novel A∗-search-based fan-in routing method with Hanan grid that fully utilizes the aligned fans and intermediate results. Experimental results demonstrate that the proposed framework achieves maximum parallelism and crossbar utilization, thereby reducing cycle counts by 19.6% and ensuring that all benchmarks map successfully under strict area constraints. We also confirm the scalability and practical applicability of the proposed framework for large-scale logic mapping in memristor-based LiM systems.

Modern computing is increasingly limited not by processing speed, but by the time and energy required to move data between memory and processors. Researchers at UNIST have developed an automated design framework that addresses this challenge by making logic-in-memory (LiM) chips more efficient.

Led by Professor Heechun Park of the Department of Electrical Engineering, the team designed a framework that automatically optimizes the placement of logic circuits and data pathways in memristor-based LiM architectures. By enabling more operations to run simultaneously while making better use of limited chip area, the approach reduced the number of computation cycles by nearly 20% compared with existing state-of-the-art methods.

Unlike conventional computer chips, LiM architectures perform computation directly where data are stored, reducing costly data movement between memory and processors. This approach helps overcome the memory wall where data transfer limits overall computing performance. 

The framework determines where computations are performed within a memristor crossbar array and how intermediate results move to the next operation. Unlike previous approaches, it enables computations to proceed in both the horizontal and vertical directions, allowing more operations to run simultaneously while making better use of the available chip area.

The framework also reorganizes intermediate data during computation, freeing unused memory cells and reducing wasted space. It then identifies efficient routes for transferring intermediate results between computational blocks, preserving parallel execution even under tight area constraints.

In benchmark evaluations, chips designed using the new framework required 19.6% fewer computation cycles than those designed using existing approaches. The framework also successfully mapped every benchmark circuit, including designs that previous methods could not accommodate under the same area constraints, suggesting it can scale to larger LiM systems.

“The performance of LiM computing depends not only on the memory device itself, but also on how computations are organized within the array,” said Professor Park. "By arranging operations to maximize parallel execution, our framework improves efficiency while remaning practical under realistic area constraints."

The research was conducted by Ikkyum Kim and Minhong Kim as first and second authors, respectively, with Professor Heechun Park serving as the corresponding author. The findings were published online in  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) on June 2, 2026.

The research was supported by the National Research Foundation of Korea (NRF) and the Institute of Information & Communications Technology Planning & Evaluation (IITP). The EDA tool was supported by the IC Design Education Center (IDEC).

Journal Reference

Ikkyum Kim, Minhong Kim, and Heechun Park, “A Parallelism-Driven, Area-Aware Technology Mapping Framework for Memristive Logic-in-Memory,”   IEEE TCAD , (2026).