Abstract

Achieving the theoretical performance of 2D molybdenum disulfide (MoS2) electronics is currently bottlenecked by interfacial contamination derived from lithographic processing. A critical, yet often overlooked, mechanism is the interaction between photoresist (PR) and plasma, which chemically alters the interface. In this work, we elucidate the atomistic origin of this degradation: theoretical calculations based on molecular dynamics (MD) and density functional theory (DFT) reveal that plasma exposure functionalizes the PR with oxygen, drastically increasing its adsorption energy on the MoS2 surface from −1.15 to −2.36 eV. This doubling of adsorption energy creates thermodynamically stable, hardened residues that resist conventional removal methods. To overcome this fundamental limitation, we introduce a universal prevention-first strategy: Sacrificial Metal Mask Lithography. By utilizing a sacrificial layer to physically isolate the channel, we shield the MoS2 from reactive plasma species, preventing the formation of hardened residue entirely. This strategy results in a ten-fold reduction in contact resistance (RC) from 2.59 × 106 Ω·µm to 2.58 × 105 Ω·µm and an order-of-magnitude enhancement in on-current. Crucially, we demonstrate the universality of this method by successfully applying it to top-gated transistor arrays, electron-beam lithography (EBL), and atomic layer deposition (ALD)-synthesized films.

Two-dimensional (2D) semiconductors, such as molybdenum disulfide (MoS2) hold promise for smaller, thinner electronics, but their extreme thinness also makes them particularly vulnerable to contamination during fabrication. Even small amounts of residue can interfere with electrical performance.

A research team, led by Professor Myung-Soo Kim of the Department of Electrical Engineering and Professor Byoung Jo Kim of the Graduate School of Semiconductor Materials and Devices Engineering at UNIST, has developed a fabrication method that protects MoS2 from photoresist (PR) residue. The approach uses a thin, removable metal layer to keep the residue from reaching the semiconductor surface.

PR is a light-sensitive material used to pattern circuits during semiconductor fabrication. When exposed to plasma, however, it can leave residue on MoS2 that conventional solvents struggle to remove. More aggressive cleaning can damage or even detach the atomically thin material from its substrate.

Rather than removing the residue after it forms, the researchers prevent it from reaching the MoS2 in the first place. They place a 5-nanometer-thick metal layer over the semiconductor before patterning. Once fabrication is complete, the metal is dissolved, carrying the accumulated residue with it.

Transistors made with the new process had a contact resistance of 2.58 × 10⁵ Ω·μm, about one-tenth that of devices made conventionally. Their on-current, or the current flowing when the transistor is switched on, increased by roughly tenfold. The researchers also found no clear damage to the crystal structure of MoS2 after the metal layer was removed.

The team also uncovered why the residue is so difficult to remove. Molecular-level calculations showed that plasma exposure introduces oxygen into the PR, changing its chemistry and causing it to bind much more strongly to MoS2. The calculated adsorption energy shifted from −1.15 to −2.36 eV, roughly doubling the strength of the interaction.

“This process can be used not only with conventional semiconductor patterning, but also with electron-beam lithography for finer features,” said Dahyun Kim, first author of the study. “We also found that it works with MoS2 produced by different synthesis methods.”

The researchers tested the method with top-gated transistor arrays, electron-beam lithography, and MoS2 films grown by atomic layer deposition, showing that it can be used across different device structures and fabrication methods.

“MoS2 is a promising material for making semiconductor devices, such as transistors smaller and thinner,” said Professor Myung-Soo Kim. “By addressing process contamination that has limited device performance, this work could help advance highly integrated logic and memory devices based on 2D semiconductors.”

The study was published online in  Small  on August 11, 2026. The research was supported by the Ministry of Science and ICT (MSIT), National Research Foundation of Korea (NRF), Institute of Information & Communications Technology Planning & Evaluation (IITP), InnoCORE program, Ministry of Trade, Industry and Energy (MOTIE), and Korea Institute for Advancement of Technology (KIAT).

Journal Reference

Dahyeon Kim, Yanfeng Zhao, Sungyeon Kim,    et al ., “Preventing Plasma-Induced Resist Hardening in Molybdenum Disulfide Transistors via Sacrificial Metal Mask Lithography,”     Small, (2026).