Two student projects from Professor Heein Yoon's lab are advancing circuit automation at different stages of the chip lifecycle—using AI to optimize analog circuit design and enabling clock circuits to recalibrate themselves as operating conditions change.

The work, conducted in the Department of Electrical Engineering, received separate honors from Samsung Electronics and the Institute for Information & Communications Technology Planning & Evaluation (IITP) in August 2026.

SungJin Kim, a Combined MS-Ph.D. student in the Department of Electrical Engineering, received an outstanding paper award from Samsung Electronics' Device Solutions (DS) Division on August 19. His research automates the design of LC voltage-controlled oscillators (LC-VCOs), key circuits for generating precise reference frequencies in wireless communications and AI chips.

LC-VCO design requires engineers to balance tightly coupled parameters affecting frequency, power consumption, and noise. Changes in fabrication technology or target frequency can therefore require extensive simulation and redesign, making the process difficult to automate.

His framework combines reinforcement learning to optimize circuit parameters with a gradient-based algorithm for physical layout. By integrating circuit and layout optimization into a single workflow, the approach reduces the manual effort involved in adapting designs to different semiconductor technologies and frequency ranges.

The approach achieved strong figures of merit (FoM) across multiple technology nodes and frequency bands. The researchers expect it to shorten development cycles and facilitate the migration of analog and RF circuits to new semiconductor processes.

“I continued working on circuit design automation because I enjoyed the research itself, even when progress was difficult to see,” said SungJin Kim. “I'm glad the work has attracted interest from designers, and I hope to continue contributing to the field.”

A second project from Professor Yoon's lab tackles automation after a circuit is already operating. On August 26, Combined MS-Ph.D. students HyeonJun Nam, Hyogyoung An, and ChangMin An, competing as team  ACELAB , received the IITP President's Award at ICT Challenge 2026 for an injection-locked clock generator that automatically adjusts its operation to suppress unwanted reference spurs.

Injection locking offers an energy-efficient way to generate the precise clock signals that coordinate operations within a chip. But injecting an external reference signal can introduce spurs around the target frequency, degrading signal quality.

The ACELAB design addresses that problem by allowing the circuit to find the injection timing that minimizes spurs. If changes in fabrication process, supply voltage, or temperature shift the optimum, an on-chip calibration circuit searches for a new operating point and adjusts accordingly. This reduces both reference spurs and clock jitter without relying on complex external control.

Such self-calibration could benefit AI accelerators, high-speed communications hardware, and next-generation systems-on-chip (SoCs), where clock quality directly affects system performance. The team plans to develop the technology into reusable clock IP for different semiconductor processes and operating frequencies.

Meanwhile, the ICT Challenge 2026 drew 206 teams from 84 research centers at 39 universities. Of the 32 teams that advanced from the preliminary round, five—including ACELAB—received the IITP President's Award. Projects were evaluated for technical performance as well as market and commercialization potential.

“We are pleased that the technical merit and potential of our research were recognized,” the ACELAB team said. “We hope to continue developing semiconductor technologies with practical applications in industry.”